The present invention relates to a shift register used in a variety of integrated circuits and the like, and more particularly, to a shift register consuming less current.
A shift register is a device for shifting an input signal in synchronization with a clock when transferring the input signal. The shift register is used in an integrated circuit, a semiconductor device and the like.
Hereinafter, the shift register used in a semiconductor memory device will be exemplarily described.
A semiconductor memory device satisfying DDR2/DDR3 specification secures a write recovery time (tWR) to ensure a complete data storage operation in a memory cell enabled by an active command. That is, a precharge operation of the cell is prohibited during the write recovery time (tWR).
In an auto precharge mode, even if a separate precharge command is not given, the precharge operation is performed at a timing defined in the specification if a column address <10> has a logic high level when a write or read command is applied. As a result of the precharge operation, an activated word line is deactivated and a bit line is precharged.
In the auto precharge mode, if a write with auto precharge command is applied, a start point of the precharge operation is determined by the write recovery time (tWR) based on the clock, which is set in a mode register set.
That is, the precharge operation is started internally after the write recovery time (tWR) from an input of the write with auto precharge command.
The shift register is used to allow the precharge operation to be performed after the write recovery time (tWR), which is based on the clock, from the input of the write command.
FIG. 1 is a circuit diagram of a conventional shift register used in a semiconductor memory device to secure a write recovery time (tWR).
Referring to FIG. 1, the conventional shift register includes a plurality of shift units 110, 120, 130, 140, 150 and 160. Each of the shift units 110 to 160 shifts an input signal by one clock pulse in synchronization with a clock CLOCK.
The input signal is a write with precharge signal INPUT that is activated when a write command is input when a column address <10> has a logic high level. The plurality of shift units 110 to 160 each shifts the write with precharge signal INPUT by one clock pulse in synchronization with the clock CLOCK.
One of output signals A, B, C, D, E and F of the plurality of shift units 110, 120, 130, 140, 150 and 160 is output as an auto precharge signal APCG. For example, when the write recovery time tWR is 3, the write with precharge signal INPUT is delayed by the three shift units 110, 120 and 130 before being output as the auto precharge signal APCG. When the write recovery time tWR is 6, the write with precharge signal INPUT is delayed by the six shift units 110, 120, 130, 140, 150 and 160 before being output as the auto precharge signal APCG. The write recovery time tWR is set at a value between 1 and 6 by signals TWR1, TWR2, TWR3, TWR4, TWR5 and TWR6 respectively.
That is, the shift register delays the write with precharge signal INPUT by the write recovery time tWR based on the clock CLOCK to output the auto precharge signal APCG.
FIG. 2 is a circuit diagram of the shift unit 110 in the conventional shift register of FIG. 1.
Referring to FIG. 2, the shift unit 110 includes two pass gates PG1 and PG2, and two latches 111 and 112. This is because the shift unit 110 is designed to shift the write with precharge signal INPUT by one clock pulse. In a case where the shift unit 110 is designed to shift the write with precharge signal INPUT by half a clock pulse, the shift unit 110 may include only one pass gate and one latch.
In operation, when the clock CLOCK has a logic low level, the first gate PG1 is turned on, and when the clock CLOCK has a logic high level, the second pass gate PG2 is turned on. Then, the write with precharge signal INPUT is sequentially shifted to the latch unit 111 and then to the next latch unit 112 every half clock pulse. Consequently, the shift unit 110 including the two pass gates PG1 and PG2 and the two latches 111 and 112 shifts the write with precharge signal INPUT by one clock pulse.
The shift unit 110 further includes a transistor 113 configured to reset the signal in the latch 111 in response to an initialization signal INITIAL.
FIG. 3 is a timing diagram illustrating an operation of the conventional shift register of FIG. 1.
For simplicity, FIG. 3 illustrates a case where the write recovery time tWR is 6. When the write with precharge signal INPUT is received, the shift register shifts the write with precharge signal INPUT by six clock pulses to output the auto precharge signal APCG. As such, the memory device can perform an auto precharge operation after the write recovery time tWR from a write operation.
As the operation speed of a memory device, semiconductor device or an integrated circuit including the shift register is increased, frequency of a clock for the shift register is also increased accordingly.
Then, the current consumption of the shift register is also increased accordingly. This is because the shift register is operated based on the clock, and thus the shift register consumes current every toggling of the clock. Therefore, there is a demand for a low power shift register consuming less current.